Method and apparatus for up-and down-conversion of radio frequency (RF) signals

ABSTRACT

This patent describes a method and system which overcomes the LO-leakage problem of direct conversion and similar RF transmitters and receivers. To solve this problem a virtual LO™ signal is generated which emulates mixing with a local oscillator (LO) signal. However, the virtual local oscillator (VLO) signal is constructed using signals that do not contain a significant amount of power (or no power at all) at the wanted output RF frequency, so there is no LO component to leak to the output. The invention also does not require sophisticated filters or large capacitors as other designs in the art, so it is fully integratable.

The present invention relates generally to communications, and morespecifically, to a fully-integrable method and apparatus for up- anddown-conversion of radio frequency (RF) and baseband signals withimproved performance.

BACKGROUND OF THE INVENTION

Many communication systems modulate electromagnetic signals frombaseband to higher frequencies for transmission, and subsequentlydemodulate those high frequencies back to their original frequency bandwhen they reach the receiver. The original (or baseband) signal, may be,for example: data, voice or video. These baseband signals may beproduced by transducers such as microphones or video cameras, becomputer generated, or transferred from an electronic storage device. Ingeneral, the high transmission frequencies provide longer range andhigher capacity channels than baseband signals, and because highfrequency RF signals can propagate through the air, they can be used forwireless channels as well as hard wired or fibre channels.

All of these signals are generally referred to as radio frequency (RF)signals, which are electromagnetic signals, that is, waveforms withelectrical and magnetic properties within the electromagnetic spectrumnormally associated with radio wave propagation. The electromagneticspectrum was traditionally divided into 26 alphabetically designatedbands, however, the International Telecommunication Union (ITU) formallyrecognizes 12 bands, from 30 Hz to 3000 GHz. New bands, from 3 THz to3000 THz, are under active consideration for recognition.

Wired communication systems which employ such modulation anddemodulation techniques include computer communication systems such aslocal area networks (LANs), point to point signalling, and wide areanetworks (WANs) such as the Internet. These networks generallycommunication data signals over electrical or optical fibre channels.Wireless communication systems which may employ modulation anddemodulation include those for public broadcasting such as AM and FMradio, and UHF and VHF television. Private communication systems mayinclude cellular telephone networks, personal paging devices, HF radiosystems used by taxi services, microwave backbone networks,interconnected appliances under the Bluetooth standard, and satellitecommunications. Other wired and wireless systems which use RF modulationand demodulation would be known to those skilled in the art.

One of the current problems in the art, is to develop physically smalland inexpensive modulation and demodulation techniques and devices thathave good performance characteristics. For cellular telephones, forexample, it is desirable to have transmitters and receivers (which maybe referred to in combination as a transceiver) which can be fullyintegrated onto integrated circuits (ICs).

Several attempts at completely integrated transceiver designs have metwith limited success. For example, most RF topology typically requiresat least two high quality filters that cannot be economically integratedwithin any modern IC technology. Other RF receiver topologies exist,such as image rejection architectures, which can be completelyintegrated on a chip, but lack in overall performance. Most receiversuse the “super-heterodyne” topology, which provides excellentperformance, but does not meet the desired level of integration formodem wireless systems.

Existing transceiver solutions and their associated problems andlimitations are summarized below.

1. Super-Heterodyne

The super-heterodyne receiver uses a two-step frequency translationmethod to convert an RF signal to a baseband signal. FIG. 1 presents ablock diagram of a typical super-heterodyne receiver 10. Generally, themixers labelled M1 12, MI 14, and MQ 16 are used to translate anincoming RF signal to baseband or to some intermediate frequency (IF).The balance of the components amplify the signal being processed andfilter noise from it.

More specifically, the RF band pass filter (BPF1) 18 first filters theincoming signal and corruptive noise coming from the antenna 20,attenuating out of band signals and passing the desired signal (notethat this band pass filter 18 may also be a duplexer). A low noiseamplifier 22 then amplifies the filtered antenna signal, increasing thestrength of the RF signal and reducing the noise figure of the receiver10. The signal is next filtered by another band pass filter (BPF2) 24usually identified as an image rejection filter. The desired signal,plus residual unwanted signals, then enter mixer M1 12 which multipliesthis signal with a periodic sinusoidal signal generated by the localoscillator (LO1) 26. The mixer M1 12 receives the signal from the imagerejection filter 24 and causes both a down-conversion and anup-conversion in the frequency domain. Usually, the down-convertedportion is retained at the so-called “Intermediate Frequency” (IF).

Generally, a mixer is a circuit or device that accepts as its input twodifferent frequencies and presents at its output:

-   (a) a signal equal in frequency to the sum of the frequencies of the    input signals;-   (b) a signal equal in frequency to the difference between the    frequencies of the input signals; and-   (c) the original input frequencies.

Note that the frequency conversion process causes a second band offrequencies to be superimposed upon the desired signal at the IFfrequency. These “image frequencies” are also passed by the band passfilter 24 and corrupt the desired signal. Note also that the typicalembodiment of a mixer is a digital switch, which may generatesignificantly more tones than those described in (a) through (c).

The IF signal is next filtered by a band pass filter (BPF3) 28 typicallycalled the channel filter, which is centered around the IF frequency,thus filtering out mixer signals (a) and (c) above.

The signal is then amplified by an amplifier (IFA) 30, and is split intoits in-phase (I) and quadrature (O) components, using mixers MI 14 andMQ 16, and orthogonal mixing signals generated by local oscillator (LO2)32 and 90 degree phase shifter 34. LO2 32 generates a regular, periodicsignal which is typically tuned to the IF frequency, so that the signalscoming from the outputs of MI 14 and MQ 16 are now at baseband, that is,the frequency at which they were originally generated. The two signalsare next filtered using low pass filters LPFI 36 and LPFQ 38 to removethe unwanted products of the mixing process, producing baseband I and Qsignals. The signals may then be amplified by gain-controlled amplifiersAGCI 40 and AGCQ 42, and digitized via analog to digital converters ADI44 and ADO 46 if required by the receiver.

The main problems with the super-heterodyne design are:

-   -   it requires expensive off-chip components, particularly band        pass filters 18, 24, 28, and low pass filters 36, 38 to remove        unwanted signal components;    -   the off-chip components require design trade-offs that increase        power consumption and reduce system gain;    -   image rejection is limited by the off-chip components, not by        the target integration technology;    -   isolation from digital noise can be a problem; and    -   it is not fully integratable.        2. Image Rejection Architectures

Several image rejection architectures exist, but are not widely used.The two most well known being the Hartley Image Rejection Architectureand the Weaver Image Rejection Architecture. There are other designs,which are generally based on these two architectures, and other methodswhich employ poly-phase filters to cancel image components. Generally,either accurate signal phase shifts or accurate generation of quadraturelocal oscillators are employed in these architectures to cancel theimage frequencies. The amount of image cancellation is directlydependent upon the degree of accuracy in producing the phase shift or inproducing the quadrature local oscillator signals.

Although the integratability of these architectures is high, theirperformance is relatively poor due to the required accuracy of the phaseshifts and quadrature oscillators. This architecture has been used fordual mode receivers on a single chip.

3. Direct Conversion

Direct conversion architectures demodulate RF signals to baseband in asingle step, by mixing the RF signal with a local oscillator signal atthe carrier frequency of the RF signal. There is therefore no imagefrequency, and no image components to corrupt the signal. Directconversion receivers offer a high level of integratability, but alsohave several important problems. Hence, direct conversion receivers havethus far proved useful only for signalling formats that do not placeappreciable signal energy near DC after conversion to baseband.

A typical direct conversion receiver is shown in FIG. 2. The RF bandpass filter (BPF1) 18 first filters the signal coming from the antenna20 (this band pass filter 18 may also be a duplexer). A low noiseamplifier 22 is then used to amplify the filtered antenna signal,increasing the strength of the RF signal and reducing the noise figureof the receiver 10.

The signal is then split into its quadrature components and demodulatedin a single stage using mixers MI 14 and MQ 16, and orthogonal signalsgenerated by local oscillator (LO2) 32 and 90 degree phase shifter 34.L02 32 generates a regular, periodic signal which is tuned to theincoming wanted frequency rather than an IF frequency as in the case ofthe super-heterodyne receiver. The signals coming from the outputs of MI14 and MQ 16 are now at baseband, that is, the frequency at which theywere originally generated. The two signals are next filtered using lowpass filters LPFI 36 and LPFQ 38, are amplified by gain-controlledamplifiers AGCI 40 and AGCQ 42, and are digitized via analog to digitalconverters ADI 44 and ADQ 46.

Direct conversion RF receivers have several advantages oversuper-heterodyne systems in term of cost, power, and level ofintegration, however, there are also several serious problems withdirect conversion. These problems include:

-   -   noise near baseband (that is, 1/f noise) which corrupts the        desired signal;    -   local oscillator (LO) leakage in the RF path that creates DC        offsets. As the LO frequency is the same as the incoming signal        being demodulated, any leakage of the LO signal onto the antenna        side of the mixer will pass through to the output side as well;    -   local oscillator leakage into the RF path that causes        desensitization. Desensitation is the reduction of desired        signal gain as a result of receiver reaction to an undesired        signal. The gain reduction is generally due to overload of some        portion of the receiver, such as the AGC circuitry, resulting in        suppression of the desired signal because the receiver will no        longer respond linearly to incremental changes in input voltage.    -   noise inherent to mixed-signal integrated circuits corrupts the        desired signal;    -   large on-chip capacitors are required to remove unwanted noise        and signal energy near DC, which makes integrability expensive.        These capacitors are typically placed between the mixers and the        low pass filters; and    -   errors are generated in the quadrature signals due to        inaccuracies in the 90 degree phase shifter.        4. Near Zero-IF Conversion

This receiver architecture is similar to the direct conversionarchitecture, in that the RF input signal band is translated broughtclose to baseband in a single step using a regular, periodic oscillatorsignal. However, the desired signal is not brought exactly to basebandand therefore DC offsets and 1/f noise do not contaminate the outputsignal. Image frequencies are again a problem though, as in the case ofthe super-heterodyne structure.

Additional problems encountered with near zero-IF architectures include:

-   -   the need for very accurate quadrature local oscillators;    -   the need for several balanced signal paths for purposes of image        cancellation;    -   noise inherent to mixed-signal integrated circuits which        corrupts the desired output signal; and    -   isolation from digital noise can be a problem.        5. Sub-Sampling Down-Conversion

This method of signal down-conversion utilizes subsampling of the inputsignal to effect the frequency translation, that is, the input signal issampled at a lower rate than the signal frequency. This may be done, forexample, by use of a sample and hold circuit.

Although the level of integration possible with this technique is thehighest among those discussed thus far, the subsampling down-conversionmethod suffers from two major drawbacks:

-   -   subsampling of the RF signal causes aliasing of unwanted noise        power to DC. Sampling by a factor of m increases the        down-converted noise power of the sampling circuit by a factor        of 2m; and    -   subsampling also increases the effect of noise in the sampling        clock. In fact, the clock phase noise power is increased by m²        for sampling by a factor of m.

There is therefore a need for a method and apparatus of modulating anddemodulating RF signals which allows the desired integrability alongwith good performance.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a novel method andsystem of modulation and demodulation which obviates or mitigates atleast one of the disadvantages of the prior art.

One aspect of the invention is broadly defined as a first signalgenerator for producing a first time-varying signal φ₁; and a secondsignal generator for producing a second time-varying signal φ₂; whereφ₁*φ₂ has significant power at the frequency of a local oscillatorsignal being emulated, and neither φ₁ nor φ₂ has significant power atthe frequency of the local oscillator signal being emulated.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the invention will become more apparent fromthe following description in which reference is made to the appendeddrawings in which:

FIG. 1 presents a block diagram of a super-heterodyne system as known inthe art;

FIG. 2 presents a block diagram of a direct conversion transmitter asknown in the art;

FIG. 3 presents a mixer and synthesizer arrangement in a broadembodiment of the invention;

FIG. 4 (a) presents a first exemplary mixer input signals pairingplotted in amplitude against time, in an embodiment of the invention;

FIG. 4 (b) presents a second exemplary mixer input signals pairingplotted in amplitude against time, in an embodiment of the invention;

FIG. 5 presents a mixer and synthesizer arrangement for modulation ordemodulation of in-phase and quadrature components of an input signal inan embodiment of the invention;

FIG. 6 presents a block diagram of an exemplary signal synthesizer in anembodiment of the invention, employing a pulse swallower and adivide-by-2 circuit;

FIG. 7 presents a logic diagram of an exemplary signal synthesizer forgenerating quadrature mixer signals, in an embodiment of the invention;

FIG. 8 presents a logic diagram of an exemplary signal synthesizer in anembodiment of the invention, employing a shift register;

FIG. 9 presents a logic diagram of an exemplary signal synthesizer in anembodiment of the invention, employing two shift registers;

FIG. 10 presents a logic diagram of an exemplary signal synthesizer inan embodiment of the invention, employing an input signal with afrequency equal to the RF carrier;

FIG. 11 presents a logic diagram of an exemplary signal synthesizer inan embodiment of the invention, employing a shift register withfeedback; and

FIG. 12 presents a block diagram of an embodiment of the inventionemploying N mixers and N time-domain signals.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to the frequency translation of RF signalsto and from baseband in highly integrated receivers and transmitters. Itis particularly concerned with the generation of signals used in thetranslation process which have properties that solve the image-rejectionproblems associated with heterodyne receivers and transmitters and theLO-leakage and 1/f noise problems associated with direct conversionreceivers and transmitters.

A circuit which addresses the objects outlined above, is presented as ablock diagram in FIG. 3. This figure presents a modulator or demodulatortopography 70 in which an input signal x(t) is mixed with twosynthesized signals (labelled φ₁ and φ₂) which are irregular and vary inthe time domain (TD), to effect the desired modulation or demodulation.The two mixers M1 72 and M2 74 are standard mixers known in the art,having the typical properties of an associated noise figure, linearityresponse, and conversion gain. The selection and design of these mixerswould follow the standards known in the art, and could be, for example,double balanced mixers. Though this figure implies various elements areimplemented in analogue form they can be implemented in digital form.

The two synthesizers 76 and 78 generate two time-varying functions φ₁and φ₂ that together comprise a virtual local oscillator (VLO) signal.These two functions have the properties that their product emulates alocal oscillator (LO) signal that has significant power at the carrierfrequency, but neither of the two signals has a significant level ofpower at the frequency of the LO being emulated. As a result, thedesired modulation or demodulation is affected, but there is no LOsignal to leak into the RF path.

The representation in FIG. 3 is exemplary, as any two-stage or multiplestage mixing architecture may be used to implement the invention. Aswell, the synthesizer for generating the time-varying mixer signals φ₁and φ₂ may be comprised of a single device, or multiple devices.

In current receiver and transmitter technology, frequency translation ofan RF signal to and from baseband is performed by multiplying the inputsignal by regular, periodic, sinusoids. If one multiplication isperformed, the architecture is said to be a direct-conversion orhomodyne architecture, while if more than one multiplication isperformed the architecture is said to be a heterodyne orsuper-heterodyne architecture. Direct-conversion transceivers sufferfrom LO leakage and 1/f noise problems which limit their capabilities,while heterodyne transceivers require image-rejection techniques whichare difficult to implement on-chip with high levels of performance.

The problems of image-rejection, LO leakage and 1/f noise in highlyintegrated transceivers can be overcome by using more complex signalsthan simple, regular, periodic, sinusoids in the frequency translationprocess. These signals have tolerable amounts of power at the RF bandfrequencies both in the signals themselves and in any other signalsproduced during their generation. Two example of such signals (φ₁ andφ₂) are presented in FIGS. 4( a) and 4(b), and are described in detailhereinafter.

The preferred criteria for selecting the functions φ₁ and φ₂ are:

-   (i) for the signal x(t) to be translated to baseband, φ₁(t)*φ₂(t)    must have a frequency component at the carrier frequency of x(t);-   (ii) in order to minimize image problems, φ₁(t)*φ₂(t) must have less    than a tolerable amount energy at frequencies other than the carrier    frequency of x(t) or at least far enough away that these image    frequencies can be significantly filtered on-chip prior to    down-conversion; and-   (iii) in order to minimize LO leakage problems, the signals φ₁ and    φ₂ must not have significant amounts of power in the RF output    signal bandwidth. That is, the amount of power generated at the    output frequency should not effect the overall system performance of    the transmitter or receiver in a significant manner;-   (iv) also to avoid LO leakage found in conventional direct    conversion and directly modulated topologies, the signals required    to generate φ₁ and φ₂ or the intermediate signals which occur,    should not have a significant amount of power at the output    frequency;-   (v) φ₂*φ₂ should not have a significant amount of power within the    bandwidth of the up-converted RF (output) signal. This ensures that    if φ₁ leaks into the input port, it does not produce a signal within    the RF signal at the output. It also ensures that if φ₂ leaks into    node between the two mixers, it does not produce a signal within the    RF signal at the output; and-   (vi) if x(t) is an RF signal, φ₁*φ₁*φ₂ should not have a significant    amount of power within the bandwidth of the RF signal at baseband.    This ensures that if φ₁ leaks into the input port, it does not    produce a signal within the baseband signal at the output.

These signals can, in general, be random, pseudo-random, periodicfunctions of time, analogue or digital waveforms.

It would be clear to one skilled in the art that virtual LO signals maybe generated which provide the benefits of the invention to greater orlesser degrees. While it is possible in certain circumstances to havealmost no LO leakage, it may be acceptable in other circumstances toincorporate virtual LO signals which still allow a degree of LO leakage.

Exemplary sets of acceptable waveforms are presented in FIGS. 4( a) and4(b), plotted in amplitude versus time. In FIG. 4( a), five cycles ofthe VLO signal are presented, labelled φ₁φ₂. It is important to notethat at no point in the operation of the circuit is an actual “φ₁φ₂”signal ever generated; the mixers receive separate φ₁ and φ₂ signals,and mix them with the input signal using different physical components.Hence, there is no LO signal which may leak into the circuit. The statesof these φ₁ and φ₂ signals with respect to the hypothetical φ₁φ₂ outputare as follows:

φ₁φ₂ φ₁ φ₂ Cycle 1 - LO HI LO Cycle 1 - HI LO LO Cycle 2 - LO HI LOCycle 2 - HI LO LO Cycle 3 - LO LO HI Cycle 3 - HI LO LO Cycle 4 - LO HILO Cycle 4 - HI LO LO Cycle 5 - LO LO HI Cycle 5 - HI HI HI

Similarly, FIG. 4( b) presents a second exemplary set of acceptablewaveforms, plotted in amplitude versus time. In this case, however, thewaveforms repeat on a four cycle pattern. The states of these φ₁ and φ₂signals with respect to the hypothetical φ₁φ₂ output are as follows:

φ₁φ₂ φ₁ φ₂ Cycle 1 - LO LO LO Cycle 1 - HI HI LO Cycle 2 - LO LO LOCycle 2 - HI HI LO Cycle 3 - LO HI HI Cycle 3 - HI LO HI Cycle 4 - LO HIHI Cycle 4 - HI LO HI

While these signals may be described as “aperiodic”, groups of cyclesmay be repeated successively. For example, the pattern of the φ₁ and φ₂input signals presented in FIG. 4( a) which generate the φ₁*φ₂ signal,repeat with every five cycles. Similarly, the pattern of the φ₁ and φ₂input signals presented in FIG. 4( b) repeat with every four cycles.Longer cycles could certainly be used.

It would be clear to one skilled in the art that many additionalpairings of signals may also be generated. The more thoroughly the abovecriteria (i)–(vi) for selection of the φ₁ and φ₂ signals are compliedwith, the more effective the invention will be in overcoming theproblems in the art.

As well, rather than employing two mixing signals shown above, sets ofthree or more may be used (additional description of this is givenhereinafter with respect to FIG. 12).

The topology of the invention is similar to that of two stage ormultistage modulators and demodulators, but the use of irregular,time-varying mixer signal provides fundamental advantages over knowntransmitters and receivers. For example:

-   -   minimal 1/f noise;    -   minimal imaging problems;    -   minimal leakage of a local oscillator (LO) signal into the RF        output band;    -   removes the necessity of having a second LO and various (often        external) filters; and    -   has a higher level of integration as the components it does        require are easily placed on an integrated circuit. For example,        no large capacitors or sophisticated filters are required.

The invention provides the basis for fully integrated communicationstransmitters and receivers. Increasing levels of integration have beenthe driving impetus towards lower cost, higher volume, higherreliability and lower power consumer electronics since the inception ofthe integrated circuit. This invention will enable communicationsdevices to follow the same integration route that other consumerelectronic products have benefited from.

Specifically, advantages from the perspective of the manufacturer whenincorporating the invention into a product include:

-   1. significant cost savings due to the decreased parts count of an    integral device. Decreasing the parts count reduces the cost of    inventory control, reduces the costs associated with warehousing    components, and reduces the amount of manpower to deal with higher    part counts;-   2. significant cost savings due to the decreased manufacturing    complexity. Reducing the complexity reduces time to market, cost of    equipment to manufacture the product, cost of testing and correcting    defects, and reduces time delays due to errors and problems on the    assembly line;-   3. reduces design costs due to the simplified architecture. The    simplified architecture will shorten the first-pass design time and    total design cycle time as a simplified design will reduce the    number of design iterations required;-   4. significant space savings and increased manufacturability due to    the high integrability and resulting reduction in product form    factor (physical size). This implies huge savings throughout the    manufacturing process as smaller device footprints enable    manufacturing of products with less material such as printed circuit    substrate, smaller product casing, and smaller final product    packaging;-   5. simplification and integrability of the invention will yield    products with higher reliability, greater yield, less complexity,    higher life span and greater robustness; and-   6. due to the aforementioned cost savings, the invention will enable    the creation of products that would otherwise be economically    unfeasible.    Hence, the invention provides the manufacturer with a significant    competitive advantage.

From the perspective of the consumer, the marketable advantages of theinvention include:

-   -   lower cost products, due to the lower cost of manufacturing;    -   higher reliability as higher integration levels and lower parts        counts imply products will be less prone to damage from shock,        vibration and mechanical stress;    -   higher integration levels and lower parts counts imply longer        product life span;    -   lower power requirements and therefore lower operating costs;    -   higher integration levels and lower parts counts imply lighter        weight and physically smaller products; and    -   the creation of economical new products.

The invention can be applied in many ways which would be clear to oneskilled in the art. A number of manners of creating VLO signals andapplying them are described hereinafter, but it is understood that theseembodiments are exemplary and not limiting.

Since the mixers in most transceivers act as solid state switches beingturning on and off, it is preferable to drive the mixers using squarewaveforms rather than sinusoids. Square waveforms with steep leading andtrailing edges will switch the state of the mixers more quickly, and ata more precise moment in time than sinusoid waveforms.

It is also important to note that in many modulation schemes, it isnecessary to modulate or demodulate both in-phase (I) and quadrature (Q)components of the input signal, which requires a modulator ordemodulator 90 as presented in the block diagram of FIG. 5. In thiscase, four modulation functions would have to be generated: φ_(1I),which is 90 degrees out of phase with φ_(1Q) and φ_(2I), which is 90degrees out of phase with φ_(2Q). The pairing of signals φ_(1I), andφ_(2I) must meet the function selection criteria listed above, as mustthe signal pairing of φ_(1Q), and φ_(2Q), The mixers 92, 94, 96, 98 arestandard mixers as known in the art.

As shown in FIG. 5, mixer M1I 92 receives the input signal x(t) andmixes it with φ_(1I); subsequent to this, mixer M2I 94 mixes signal x(t)φ_(1I) with φ_(2I) to yield the in-phase component of the input signal,that is, x(t) φ_(1I)φ_(2I). A complementary process occurs on thequadrature side of the demodulator, where mixer M1Q 96 receives theinput signal x(t) and mixes it with φ_(1Q); after which mixer M2Q 98mixes signal x(t) φ_(1Q) with φ_(2Q) to yield the quadrature phasecomponent of the input signal, that is, x(t) φ_(1Q) φ_(2Q). Several ofthe synthesizer 76, 78 designs presented herein produce in-phasecomponents only, but it would be clear to one skilled in the art how togenerate complementary quadrature mixing signal pairs. Generally,separate in-phase and quadrature channels have not been identified inthe interests of simplicity.

Several methods of generating such VLO signals are presented in FIGS. 6through 10. Since the LO-leakage problem can occur when power isgenerated at frequencies in the RF band anywhere on chip, it ispreferable that condition (iv) stated above be followed for intermediatesignals produced during the generation of the signals φ₁ and φ₂.However, since the leakage path to these intermediate signals oftenprovide some isolation, in such a case the condition on the intermediatesignals can be somewhat relaxed.

The synthesizer 100 presented in FIG. 6 uses an input square wave (2LO)at twice the frequency of the RF carrier of the signal being modified bya signal denoted as S. Signal S could be the signal being modified,provided the criteria for the φ₁ and φ₂ signals are met, thoughgenerally it will be an independently generated control signal. Thiscontrol signal S could also be generated using a delta-sigma (Δ-S)modulator which is known in the art.

A pulse swallower 102 is then used to remove pulses from the 2LO squarewave. The pulse swallower 102 is controlled by the input signal S, suchthat when the input signal, S, switches state, a pulse is removed fromthe 2LO signal. The resulting signal is then passed through adivide-by-2 circuit 104 to produce the φ₁(t) output signal. The inputsignal S passes through a delay circuit 106 which delays it by theamount of time it takes the 2LO signal to propagate through to the φ₁(t)output, so that the two signals are synchronized. The output of thisdelay circuit 106 is the φ₂(t) mixer signal.

Assuming that the input signal S follows no regular pattern the outputsignals φ₁(t) and φ₂(t) could be random or pseudo-random. Since thiscircuit uses an oscillator at twice the carrier frequency of the inputsignal, there is no LO signal to leak to the output or into other partsof the circuit. Similarly, none of the intermediate signals, nor eitherof the mixer signals φ₁ and φ₂, has an LO frequency component.

A logic circuit that performs the function of FIG. 6 is presented inFIG. 7. The pulse swallower 102 consists of a standard delay latch(D-latch) D1. A D-latch is a flip-flop whose input passes to the outputafter one clock cycle. The triggering of the pulse swallower 102 iscontrolled by D-latches D4 through D7 and the exclusive OR (XOR) gateXOR1, which detect the leading edge of the input signal S and create apulse which causes D1 to swallow a pulse of the input signal 2LO.D-latches D2 and D3 form a divide-by-two circuit 104 that receives theoutput of D1 and produces the φ₁ mixing signal. The D-latches D4 throughD7 also delay the S signal to produce the φ₂ signal. Note that thiscircuit produces both the I and Q components of φ₁ and φ₂, which wouldbe required for input to a mixer such as that of FIG. 5; subscriptsindicate the signals required for the frequency translation of thein-phase and quadrature components of the input signal S, respectively.

FIG. 8 presents another method for producing the signals φ₁ and φ₂.Here, the D-latches D8 through D13 form a shift register which isclocked by the signal 2LO. The signal 2LO is once again a square wavethat has a frequency of twice the RF carrier frequency. The shiftregister can be initially loaded with a predetermined sequence and theoutput φ₁ will cycle through that sequence producing the desired output.The second output φ₂ is then produced by taking the output ofconsecutive taps from the shift register, and exclusive-ORing themtogether with gate XOR2 to produce a signal that can be used to clock asecond shift register (D14 and D15). The output of the second shiftregister is then φ₂.

FIG. 9 shows a method similar to that of FIG. 8, except that signal φ₂is generated by a second shift register (D22 through D27), which is aduplicate of the shift register that produces the signal φ₁ (D16 throughD21). As well, there is a difference in the initial loading of the shiftregisters; the first shift register being loaded with the sequence thatwill produce φ₁, and the second being loaded with the sequence whichwill produce φ₂.

The previous methods of generating φ₁ and φ₂ use an input signal attwice the RF carrier frequency (that is, 2LO). In some situations it maybe difficult to design logic to operate at this frequency. If enoughisolation can be obtained to protect an input of LO from leaking intothe RF band, the method shown in FIG. 10 can be used.

Here the edges of the input signal S are aligned with the LO input edgesthrough the D flip-flop D28. The inverter I1 adds a delay to the LOinput to make sure the two signal edges remain aligned. The two signalsare then passed through an exclusive OR (XOR) gate XOR3 to produce theoutput signal φ₁. Another delay is added to the output of the D28 latchvia invertor I2 to keep the edges aligned with the output of the XORgate XOR3. The output of I2 is then φ₂.

The signal φ₂ can also be generated by using a shift register withfeedback similar to those used in the generation of PN sequences for usein spread-spectrum communications. An example of such a shift registeris shown in FIG. 11. The D-latches D29 through D32 form a shift registerwhich is clocked by the signal at twice the RF carrier frequency. MOD1does a modulo-2 multiplication of the output of D31 with the output ofD32, which is then fed into the input of D32 to produce the requiredfeedback. The signal φ₂ is then produced at the output of D32. A similarshift register with similar feedback can be used to produce the signalφ₁. The conditions on the design of these shift registers are that theyproduce the signals φ₁, and φ₂ that have the properties mentioned above:

-   -   φ₁(t)*φ₂(t) must have a frequency component at the RF carrier        frequency;    -   φ₁(t)*φ₂(t) must not contain a significant amount of power at        frequencies other that the RF carrier frequency; and    -   φ₁(t) and φ₂(t) must not contain a significant amount of energy        in the RF signal bandwidth.

The signals of the invention may also be generated in many other ways,which would be clear from the teachings herein. For example, φ₁ could begenerated using a control signal S to selectively divide a 2LO signal byeither 2 or by 4. In this case, if the value of S is a digital “0” thenthe 2LO signal could be divided by 2, and if the value of S is a digital“1”, the 2LO signal could be divided by 4. The function φ₂ can bederived from the control signal S in a similar manner, to generate apair of time-varying signals which meet the criteria of the invention tothe extent required by the application.

The invention allows one to fully integrate a RF transmitter on a singlechip without using external filters, while furthermore, the RFtransmitter can be used as a multi-standard transmitter.

The construction of the necessary logic to generate the mixing signalsof the invention would be clear to one skilled in the art from thedescription herein. Such signals may be generated using basic logicgates, field programmable gate arrays (FPGA), read only memories (ROMs),micro-controllers or other devices known in the art. Though the figuresherein imply the use of analogue components, all embodiments can beimplemented in digital form.

It would be clear to one skilled in the art that many variations may bemade to the designs presented herein, without departing from the spiritof the invention. One such variation to the basic structure in FIG. 3 isto add a filter between the two mixers 72 and 74 to remove unwantedsignals that are transferred to the output port. This filter may be alow pass, high pass, or band pass filter depending on the transmitterrequirements, and may be purely passive, or have active components.

In FIG. 3, two mixer signals are used to perform the down-conversion orup-conversion of x(t). It is also possible to use more than two signalsto accomplish the same goal. The block diagram of FIG. 12 presents sucha variation, where several functions φ₁, φ₂, φ₃ . . . φ_(n) are used togenerate the virtual LO. Here, φ₁*φ₂* . . . *φ_(n) has a significantpower level at the LO frequency being emulated, but each of thefunctions φ₁ . . . φ_(n) contain an insignificant power level at LO.Each of these methods of signal generation can be easily extended toproduce more than two signals.

The electrical circuits of the invention may be described by computersoftware code in a simulation language, or hardware development languageused to fabricate integrated circuits. This computer software code maybe stored in a variety of formats on various electronic memory mediaincluding computer diskettes, CD-ROM, Random Access Memory (RAM) andRead Only Memory (ROM). As well, electronic signals representing suchcomputer software code may also be transmitted via a communicationnetwork.

Clearly, such computer software code may also be integrated with thecode of other programs, implemented as a core or subroutine by externalprogram calls, or by other techniques known in the art.

The embodiments of the invention may be implemented on various familiesof integrated circuit technologies using digital signal processors(DSPs), microcontrollers, microprocessors, field programmable gatearrays (FPGAs), or discrete components. Such implementations would beclear to one skilled in the art.

The invention may be applied to various communication protocols andformats including: amplitude modulation (AM), frequency modulation (FM),frequency shift keying (FSK), phase shift keying (PSK), cellulartelephone systems including analogue and digital systems such as codedivision multiple access (CDMA), time division multiple access (TDMA)and frequency division multiple access (FDMA).

The invention may be applied to such applications as wired communicationsystems include computer communication systems such as local areanetworks (LANs), point to point signalling, and wide area networks(WANs) such as the Internet, using electrical or optical fibre cablesystems. As well, wireless communication systems may include those forpublic broadcasting such as AM and FM radio, and UHF and VHF television;or those for private communication such as cellular telephones, personalpaging devices, wireless local loops, monitoring of homes by utilitycompanies, cordless telephones including the digital cordless Europeantelecommunication (DECT) standard, mobile radio systems, GSM and AMPScellular telephones, microwave backbone networks, interconnectedappliances under the Bluetooth standard, and satellite communications.

While particular embodiments of the present invention have been shownand described, it is clear that changes and modifications may be made tosuch embodiments without departing from the true scope and spirit of theinvention.

1. A synthesizer for gene signals to be input to successive mixers for modulating or demodulating an input signal x(t), emulating the mixing of said input signal x(t) with a local oscillator signal having frequency f, said synthesizer comprising: a first signal generator for producing a first mixing signal φ1, which varies irregularly over time; and a second signal generator for producing a second mixing signal φ2 which varies irregularly over time; where: φ1*φ2 has significant power at the frequency f of said local oscillator signal being emulated; neither φ1 nor φ2 has significant power at the frequency f of said local oscillator signal being emulated, and said mixing signals φ1 and φ2 are designed to emulate said local oscillator signal having frequency f, in a time domain analysis.
 2. The synthesizer of claim 1, wherein signals used to generate φ1 and φ2 do not have a significant amount of power at the frequency designed to be output from said successive mixers in output signal x(t)φ1φ2.
 3. An integrated circuit comprising the synthesizer of claim
 1. 4. The synthesizer of claim 2, wherein φ1*φ1*φ2 does not have a significant amount of power within the bandwidth designed to be output from said successive mixers, in said output signal x(t)φ1φ2.
 5. The synthesizer of claim 4, wherein φ2*φ2 does not have a significant amount of power within the bandwidth designed to be output from said successive mixers in said output signal x(t)φ1φ2.
 6. The synthesizer of claim 5, wherein said first and second mixing signals φ1 and φ2 are generated using a single time base.
 7. The synthesizer of claim 5, wherein said first and second mixing signals φ1 and φ2 are digital waveforms.
 8. The synthesizer of claim 5, wherein said first and second mixing signals φ1 and φ2 are square waveforms.
 9. The synthesizer of claim 5, wherein said mixing signal φ2 is a square wave.
 10. The synthesizer of claim 5, wherein said mixing signals φ1 and φ2 effect the of an in-phase component of said input signal x(t), and a complementary pair of successive mixers with mixing signals 90 degrees out of phase, are used to effect the modulation of a quadrature component of said input signal x(t).
 11. The synthesizer of claim 5, wherein said first and second mixing signals φ1 and φ2 are periodic functions of time.
 12. The synthesizer of claim 5, wherein said first and second signal generators comprise: pulse removal means for removing pulses from a local oscillator signal which has a frequency of twice the RF carrier, generating said first mixing signal φ1; and complementary means for generating said second mixing signal φ2.
 13. The synthesizer of claim 5, wherein said pulse removal means comprises: a pulse swallower for receiving an oscillator signal at twice the frequency of the local oscillator signal being emulated, and swallowing each pulse with a control signal S; and a divide by two circuit for receiving and dividing said pulse swallowed signal by two, producing said first mixing signal φ1.
 14. The synthesizer of claim 13, wherein said complementary means comprises: a delay circuit for receiving and delaying said control signal S to be synchronized in time with said first mixing signal φ1, output said delayed control signal S as said second mixing signal φ2.
 15. The synthesizer of claim 13, wherein said control signal S comprises a periodic signal.
 16. The synthesizer of claim 13, comprising: a delta-sigma (Δ-S) modulator for generating said control signal S.
 17. The synthesizer of claim 5, wherein said first and second signal generators comprise: shift register means for generating said first and second mixing signals φ1 and φ2 by shifting out corresponding predetermined sequences.
 18. The synthesizer of claim 17, wherein said shift register means comprises: a shift register for receiving an oscillator signal at twice the frequency of the local oscillator signal being emulated, and generating said first mixing signal φ1, by shifting out a predetermined sequence.
 19. The synthesizer of claim 18, wherein said second signal generator comprises: an exclusive-OR (XOR) circuit for comparing outputs of consecutive latches in said shift register, and a second shift register being clocked by said XOR output, and generating said second mixing signal φ2, by shifting out a second predetermined sequence.
 20. The synthesizer of claim 18, wherein said second signal generator comprises: a third shift register for receiving said oscillator signal at twice the frequency of the local oscillator signal being emulated, and generating said second mixing signal φ2, by shifting out a predetermined sequence.
 21. The synthesizer of claim 5, wherein said first and second signal generators comprise: means for generating said first mixing sigal φ1, from an oscillator signal at the frequency of the local oscillator signal being emulated, and a control signal S having edges aligned with said oscillator signal; and means for delaying said control signal S to produce said second mixing signal φ2.
 22. The synthesizer of claim 21, wherein said means for delaying comprises: a delay latch for sampling said control signal S at the frequency of the local oscillator signal being emulated; and an invertor for receiving and inverting said delay latched control signal S to produce said second mixing signal φ2.
 23. The synthesizer of claim 22, wherein said means for generating said first mixing signal φ1, comprises: a second invertor for receiving the oscillator signal at the frequency of the local oscillator signal being emulated; and an exclusive-OR (XOR) circuit for comparing said inverted oscillator signal with said latched input signal x(t), producing said first mixing signal φ1.
 24. The synthesizer of claim 5, wherein said first signal generator comprises: a shift register with a feedback loop.
 25. The synthesizer of claim 24, wherein said first signal generator comprises: a shift register for receiving an oscillator signal at twice the frequency of the local oscillator signal being emulated, and generating said first mixing signal φ1, by shifting out a predetermined sequence; and a modulo-2 multiplier for receiving said first mixing signal φ1, and the output of an earlier latch in said shift register, feeding an output into a later latch in said shift register.
 26. The synthesizer of claim 5 comprising: one or more additional signal generators for producing one or more additional mixing signals, varying irregularly over time; where the product of all of said mixing signals has significant power at the frequency of a local oscillator signal being emulated, and none of said all of said mixing signals has significant power at the frequency of said local oscillator signal being emulated.
 27. The synthesizer of claim 5, where said first signal generator comprises: a divide by 2 circuit ft receiving an oscillator signal at the frequency of the local oscillator signal being emulated; and a divide by 4 circuit for receiving said oscillator signal at the frequency of the local oscillator signal being emulated; selector means for routing either the output of said divide by 2 circuit or said divide by 4 circuit to an output, said output producing said first mixing signal φ1.
 28. The synthesizer of claim 5 comprising: first and second latches which are clocked via a common clock, to align said first and second mixing signals φ1 and φ2.
 29. The synthesizer of claim 5, wherein the patterns of said first and second mixing signals φ1 and φ2 are different from one another. 